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Getting began in structured meeting in complicated SoC designs

The mixing stage of a system-on-chip (SoC) is outlined in RTL, identical to the remainder of the design. Traditionally, RTL has been constructed by means of textual content editors. Nevertheless, a decade or extra in the past, the sheer complexity of that process for the biggest SoCs grew to become unmanageable; now, most SoCs cross that threshold. Why is that this? The variety of IPs within the SoC is actually an element, and the variety of connections explodes on the integration stage. For instance, a single AXI channel connection can have 25 alerts. Subsequent, AMBA to AMBA connections in a number of flavors proliferate throughout designs.

Additionally, designers should embrace the combination infrastructure—clocks, resets, energy administration and take a look at—which should evolve because the design progresses. These necessities can add as much as 10,000 connections in an unexceptional SoC. Connections between IPs could have lots of of ports with a number of configuration tie-off choices. These ports could also be left open or related and have many different important issues. Typical interconnect complexity is clear even in a small subset of the design, as proven in Determine 1.

Determine 1 A top-level view of an SoC that makes use of FlexNoC interconnect. Supply: Arteris IP

It’s not humanly doable to immediately handle RTL at a stage the place a single IP instantiation could span lots of of strains. For this reason groups constructing giant SoCs have turned to structured meeting strategies during the last decade. The output continues to be the identical, an RTL top-level netlist, however is constructed with instruments and strategies designed to massively simplify duties’ meeting, refinement and replace by means of abstraction and automation. These instruments generally use the IP-XACT normal, an XML-based format initially developed by Accellera, now supported as IEEE 1685.

There are different collateral advantages to adopting this circulate that might be expanded in later blogs. That features robotically producing a full and detailed reminiscence map for the SoC and documentation inserts for reminiscence maps, clock knowledge, and others. This offers monitoring necessities traceability from idea by means of signoff.

Assembling an SoC

A central element of simplifying the meeting process is in bus protocol abstraction in order that an AXI bus, for instance, is handled as a single connection. IP-XACT offers normal definitions for a number of protocols. These could be prolonged, and new protocols or bundles can be outlined. A second key element is automation by means of scriptable definition of cases, ports, connections, and hierarchy.

Scripts can outline and entry a richer set of properties than generally present in RTL descriptions. These can embrace grasp/slave sort for an interface or sign sort—clock, reset and knowledge— for a port. This text reveals Python script examples. The programming language Tcl can also be supported.

The method is simple to know. The IPD platform offers a wealthy API by means of which objects could be created, deleted and modified. Properties could be accessed to information scripting. Determine 2 illustrates a few easy routines so as to add cases and ports to the present design object.

Determine 2 Features so as to add cases and ports to the present design object. Supply: Arteris IP

Embedding the design description in Python permits for highly effective user-defined automation. Any facet of the circuit amenable to a procedural definition could be automated with a process quite than outlined by means of linear instantiations and connections, as in Determine 2. A typical method in SoC meeting is to make use of connect-by-name, particularly in connecting IP bus interfaces to the corresponding bus material occasion. An instance of automating this connection is proven in Determine 3.

Determine 3 A view of features to automate bus interface connections. Supply: Arteris IP

Automated checking also can confirm this meeting course of, guaranteeing that errors are caught all through building. A Python operate to automate this process is kind of straightforward to outline. A extra complicated instance is perhaps injecting energy administration cases and connections. That is one other well-defined but concerned process open to procedural automation. Most necessary, when suitably debugged, these procedures is not going to want to vary because the design evolves, even throughout households of designs. Procedural automation can considerably summary practical complexity from SoC meeting.


Arteris IP’s IPD platform can be utilized in command line interface (CLI) or GUI mode. The GUI mode could be fairly helpful in coaching, reviewing and debugging. The CLI mode will most likely be extra closely utilized in manufacturing design flows, batch creation, regressions, and steady integration and deployment. On this article, the main focus is on CLI mode. Python scripts could be provided immediately as enter following the CLI command to start out the platform shell.

Scripts will create/modify/replace an IP-XACT database for the design. These could be folded into an information administration system alongside some other design collateral. From the IP-XACT database, a netlist could be generated in Verilog, SystemVerilog or VHDL at no matter stage the design has developed. This step will write a simulation/implementation-ready netlist all the way down to any leaf-level IP and a software command script that can add acceptable library choices to include the mandatory IP design RTL.

Incorporating legacy knowledge

Not all IPs include IP-XACT fashions; generally, in-house IPs are sometimes constructed earlier than structured meeting choices are thought of. The IPD platform offers an import possibility to simply construct such fashions from the present IP collateral.

This selection can learn RTL in a number of codecs and construct an IP-XACT mannequin referencing the RTL and protocol interface definitions. Since native naming conventions can differ intimately from normal naming, this step is often executed by means of the GUI, permitting for person steerage in mapping between native port and normal protocol names. It additionally permits user-guided sign typing. The importer is not going to solely deal with legacy IPs; it might probably import legacy designs in assist of spinoff growth in structured meeting. Determine 4 illustrates choices obtainable on this import functionality.

Determine 4 The block diagram reveals the Arteris SoC packaging circulate. Supply: Arteris IP

For many IPs, ranging from simulation command-line controls, it might be shocking to search out this step taking quite a lot of minutes per IP. Import solely must be carried out as soon as the design modifications. Because the scripting permits for automation and modifications, rework could be diminished when re-importing and updating IP. Additional data could be added later to the mannequin, similar to register maps for the IP. That matter might be coated within the subsequent article.

Scalable SoC meeting

Most design groups would agree that hand-crafting RTL for the highest stage of an SoC is not sensible. The one query is, what ought to substitute that technique? In-house scripting was one early answer however has created extra overhead in constructing and sustaining these scripts. A greater strategy is to combine by means of the automated meeting platform.

This offers a stable base for growth and a rising listing of purposes supporting automated meeting whereas permitting important design creativity in scripting differentiated automation. This platform offers actual differentiation in assist of superior design architectures for energy, reminiscence administration items (MMU), security, and safety administration. Be taught extra in regards to the Arteris IP IPD platform right here.

Tim Schneider, senior purposes engineer at Arteris IP, has over 25 years of working expertise with main corporations to confirm high-performance SoC designs.

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